ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 106

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

20.6
External Protection Input
The External Protection Input disables both FETs (Charge FET and Discharge FET) immedi-
ately (asynchronously) when the voltage on PC1 is pulled high (logic ‘1’) by the External
Protection circuitry. It is also used to disable DUVR mode if DUVR mode is enabled. Note that,
unlike a Battery Protection event, the External Protection input does not affect the status of the
FCSR (CFE, DFE, DUVRD) bits. When the ‘high’ condition disappears, the FET disabling is
released immediately. DUVR mode is automatically re-entered if enabled.
The feature is automatically enabled when the chip starts up, and can be disabled before lock-
ing the BPCR register. When locking the BPCR register, the External Protection feature is also
locked. The feature should be disabled if it is not used.
When External Protection Input is enabled, an override enable signal is set to PC1, configuring
the pin as digital input. The port may be set up to give an interrupt when the pin value
changes. The protection status can be read from the port register.
Note that the External Protection Input is default enabled. This means that after reset (and
during reset) the port is default overridden to External Protection Input, independent of the port
register setting. The user must disable the External Protection Input before the port can be
used as a normal port.
It is recommended that the external interrupt on the External Protection Input port (PC1) is
configured to ‘any edge’ to generate an interrupt to the microcontroller when using this feature,
indicating that the FET protection status has changed. Refer to
”External Interrupt” on page
53. By reading the pin register, the External Protection status can be determined. If the pin
register is set, it means that External Protection is triggered and the FET control signals
(FCSR (CFE, DFE and DUVRD)) are overridden so the FETs are disabled. In the opposite
case External Protection violation is not present.
To ensure a safe exit from the External Protection Input condition, the FETs and DUVR mode
should be disabled by SW when an External Protection condition is detected. This enables
software to control completely when the FETs are switched ON again.
If not disabled by SW, the FETs will be re-enabled once the External Protection condition dis-
appears (PC1 pin equals '0'). This feature may be useful to filter out glitches on the PC1 pin,
for instance caused by temporary high voltages on the BATT pin when connecting a charger
(refer to
”Operating Circuit” on page
141). In this case, SW does not have to take any action to
re-enable the FETs.
Note however that compared to SW switching on the FETs, the switch ON time for the FETs is
multiplied by a factor 10 when the FETs are disabled and re-enabled by External Protection
Input and the chip is operated in sleep mode. This is caused by the internal clock system and
power saving functions of the chip. For this reason, if the switch ON time of the transistors is
critical, External Interrupt on PC1 should always be enabled when using the External Protec-
tion Input feature. The interrupt should be configured to trig on any edge and will ensure that
the chip wakes up from sleep and thus enables a normal switch ON time for the FETs. To
ensure a fast rise time on the OC and OD pins, SW must either remain in ACTIVE or IDLE
mode during FET charging or disable and re-enable the OC/OD bits before entering Power-
save sleep mode. For an example on correct External Protection Input usage, refer to
Figure
20-1.
ATmega4HVD/8HVD
106
8052B–AVR–09/08