ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 123

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

23.5.1
23.5.2
23.5.3
23.5.4
8052B–AVR–09/08
EEPROM Write Prevents Writing to SPMCSR
Setting the Lock Bits from Software
Reading the Fuse and Lock Bits from Software
Preventing Flash Corruption
Note that an EEPROM write operation will block all software programming to Flash. Reading
the Fuses and Lock bits from software will also be prevented during the EEPROM write opera-
tion. It is recommended that the user checks the status bit (EEWE) in the EECR Register and
verifies that the bit is cleared before writing to the SPMCSR Register.
To set the Lock Bits, write the desired data to R0. If bits 1..0 in R0 are cleared (zero), the cor-
responding Lock bit will be programmed if an SPM instruction is executed within four cycles
after RFLB and SPMEN are set in SPMCSR. The Z-pointer is don’t care during this operation,
but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used
for reading the lOck bits). For future compatibility it is also recommended to set bit 7..2 in R0 to
“1” when writing the Lock bits. When programming the Lock bits the entire Flash can be read
during the operation.
See
Lock bits affect the Flash access.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruc-
tion is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR,
the value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN bits
will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed
within three CPU cycles or no SPM instruction is executed within four CPU cycles. When
RFLB and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB
and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after
the RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will
be loaded in the destination register as shown below. Refer to
detailed description and mapping of the Fuse Low byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
During periods of low V
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the Flash requires a minimum voltage to operate correctly. Sec-
Bit
R0
Bit
Rd
Bit
Rd
Table 24-1 on page 129
FLB7
7
1
7
–
7
CC
FLB6
, the Flash program can be corrupted because the supply voltage is
6
–
6
6
1
and
FLB5
Table 24-2 on page 129
5
5
1
5
–
FLB4
4
–
4
1
4
FLB3
3
–
3
1
3
ATmega4HVD/8HVD
for how the different settings of the
FLB2
2
–
2
2
1
Table 24-4 on page 130
FLB1
LB2
LB2
1
1
1
FLB0
LB1
LB1
0
0
0
for a
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