ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 92

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

17.5
17.6
92
ADC Voltage Reference
ADC Noise Canceler
ATmega4HVD/8HVD
Figure 17-2. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 17-3. ADC Timing Diagram, Single Conversion
Table 17-1.
The reference voltage for the ADC (V
The ADC features a noise canceler that enables conversion during sleep mode to reduce
noise induced from the CPU core and other I/O peripherals. The noise canceler can be used
with Idle mode. To make use of this feature, the following procedure should be used:
1. Make sure that the ADC is enabled and is not busy converting and the ADC conversion
2. Enter ADC Noise Reduction mode. The ADC will start a conversion once the CPU has
3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt
Condition
First conversion
Normal conversions
complete interrupt is enabled.
been halted.
will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
ADC Conversion Time, except VTEMP input.
1
1
2
MUX
Update
2
MUX
Update
14
3
15
Sample & Hold
4
16
5
REF
from Start of Conversion)
17
Sample & Hold (Cycles
) is taken from the internal 1.1V bandgap reference.
6
Sample & Hold
18
First Conversion
19
7
One Conversion
15.5
20
1.5
8
21
9
22
10
Conversion
Complete
23
11
24
Conversion
Complete
12
25
Conversion Time (Cycles)
26
13
27
Sign and MSB of Result
Sign and MSB of Result
LSB of Result
Next Conversion
1
27
13
Next
Conversion
8052B–AVR–09/08
1
LSB of Result
2
MUX
Update
2
MUX
Update
3
3