ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 82

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

16.9
82
Accessing Registers in 16-bit Mode
ATmega4HVD/8HVD
Figure 16-7. Timer/Counter Timing Diagram, with Prescaler (f
Figure 16-8 on page 82
Figure 16-8. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f
Figure 16-9 on page 82
Figure 16-9. Timer/Counter Timing Diagram, CTC mode, with Prescaler (f
In 16-bit mode (the TCWn bit is set to one) the TCNTnH/L and OCRnA/B or TCNTnL/H and
OCRnB/A are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus.
The 16-bit register must be byte accessed using two read or write operations. The 16-bit
Timer/Counter has a single 8-bit register for temporary storing of the high byte of the 16-bit
access. The same temporary register is shared between all 16-bit registers. Accessing the low
byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written
by the CPU, the high byte stored in the temporary register, and the low byte written are both
copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is
read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the
same clock cycle as the low byte is read.
TCNTn
(clk
TOVn
TCNTn
(clk
OCRnx
clk
TCNTn
(CTC)
OCFnx
clk
(clk
OCRnx
OCFnx
clk
clk
clk
clk
I/O
PCK
I/O
Tn
I/O
PCK
Tn
/8)
I/O
Tn
/8)
/8)
OCRnx - 1
MAX - 1
TOP - 1
shows the setting of OCFnA and the clearing of TCNTn in CTC mode.
shows the setting of OCFnA and OCFnB in Normal mode.
OCRnx
MAX
TOP
OCRnx Value
TOP
OCRnx + 1
BOTTOM
BOTTOM
clk_I/O
/8)
clk_I/O
BOTTOM + 1
BOTTOM + 1
OCRnx + 2
8052B–AVR–09/08
/8)
clk_I/O
/8)