ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 27

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

8.12
8.12.1
8.12.2
8052B–AVR–09/08
OSI – Oscillator Sampling Interface
Features
Overview
•
•
•
•
The Oscillator Sampling Interface (OSI) enables sampling of the Slow RC and Ultra Low
Power RC (ULP) oscillators in ATmega4HVD/8HVD. OSI can be used to calibrate the Fast RC
Oscillator runtime with high accuracy. OSI can also provide an accurate reference for compen-
sating the ULP Oscillator frequency drift.
The prescaled oscillator phase can be continuously read by the CPU through the OSICSR
register. In addition, the input capture function of Timer/Counter0 can be set up to trigger on
the rising edge of the prescaled clock. This enables accurate measurements of the oscillator
frequencies relative to the Fast RC Oscillator.
A simplified block diagram of the Oscillator Sampling Interface is shown in
Figure 8-2.
Note:
The osi_posedge signal pulses on each rising edge of the prescaled Slow RC/ ULP oscillator
clock. This signal is not directly accessible by the CPU, but can be used to trigger the input
capture function of Timer/Counter0. Using OSI in combination with the input capture function
of Timer/Counter0 facilitates accurate measurement of the oscillator frequencies with a mini-
mum of CPU calculation. Refer to
to enable the Input Capture function.
Runtime selectable oscillator input (Slow RC or ULP RC Oscillator)
7 bit prescaling of the selected oscillator
Software read access to the phase of the prescaled clock
Input capture trigger source for Timer/Counter0
Power RC
Ultra Low
Oscillator
Oscillator
Slow RC
1. One prescaled Slow RC/ULP oscillator period corresponds to 128 times the actual Slow
RC/ULP oscillator period.
Oscillator Sampling Interface Block Diagram.
OSISEL0
7 bit prescaler
”Timer/Counter(T/C0,T/C1)” on page 74
Databus
OSICSR
(1)
ATmega4HVD/8HVD
Detector
Oscillator
Fast RC
Edge
Figure
for details on how
osi_posedge
8-2.
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