ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 17
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ATMEGA8HVD-4MX
Manufacturer Part Number
ATMEGA8HVD-4MX
Description
MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA8HVD-4MX.pdf
(168 pages)
Specifications of ATMEGA8HVD-4MX
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 2.4 V
Data Converters
A/D 1x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
18-MLF® Exposed Pad (Staggered Leads), DFN
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
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7.6
7.6.1
7.6.2
8052B–AVR–09/08
Register Description
EEARL – The EEPROM Address Register
EEDR – The EEPROM Data Register
tions. Refer to the instruction set section for more details. When using the I/O specific
commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these
addresses. The ATmega4HVD/8HVD is a complex microcontroller with more peripheral units
than can be supported within the 64 location reserved in Opcode for the IN and OUT instruc-
tions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the status flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can there-
fore be used on registers containing such status flags. The CBI and SBI instructions work with
registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega4HVD/8HVD contains three General Purpose I/O Registers. These registers can
be used for storing any information, and they are particularly useful for storing global variables
and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are
directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
• Bits 7:0 – EEAR7:0: EEPROM Address
The EEPROM Address Registers – EEARL specify the EEPROM address in the 256 bytes
EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 255. The
initial value of EEARL is undefined. A proper value must be written before the EEPROM may
be accessed.
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEARL Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEARL.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
EEAR7
MSB
R/W
R/W
X
7
7
0
EEAR6
R/W
R/W
6
X
6
0
EEAR5
R/W
R/W
X
5
5
0
EEAR4
R/W
R/W
4
X
4
0
EEAR3
R/W
R/W
X
3
3
0
ATmega4HVD/8HVD
EEAR2
R/W
R/W
X
2
2
0
EEAR1
R/W
R/W
X
1
1
0
EEAR0
R/W
LSB
R/W
X
0
0
0
EEARL
EEDR
17
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