ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 81

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

16.7.1
16.7.2
16.8
8052B–AVR–09/08
Timer/Counter Timing Diagrams
Compare Match Blocking by TCNT0 Write
Using the Output Compare Unit
OCFnA as there is only one Output Compare Unit. If the corresponding interrupt is enabled,
the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag
is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared
by software by writing a logical one to its I/O bit location.
block diagram of the Output Compare unit.
Figure 16-5. Output Compare Unit, Block Diagram
All CPU write operations to the TCNTnH/L Register will block any Compare Match that occur
in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnA/B to
be initialized to the same value as TCNTn without triggering an interrupt when the
Timer/Counter clock is enabled.
Since writing TCNTnH/L will block all Compare Matches for one timer clock cycle, there are
risks involved when changing TCNTnH/L when using the Output Compare Unit, independently
of whether the Timer/Counter is running or not. If the value written to TCNTnH/L equals the
OCRnA/B value, the Compare Match will be missed.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
The figure shows the count sequence close to the MAX value.
Figure 16-6. Timer/Counter Timing Diagram, no Prescaling
Figure 16-7 on page 82
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
Figure 16-6 on page 81
shows the same timing data, but with the prescaler enabled.
MAX - 1
OCRnx
=
contains timing data for basic Timer/Counter operation.
(8/16-bit Comparator )
DATA BUS
OCFnx (Int.Req.)
MAX
ATmega4HVD/8HVD
Figure 16-5 on page 81
BOTTOM
TCNTn
Tn
) is therefore shown as a
BOTTOM + 1
shows a
81