ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 77

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

16.5.1
16.5.2
16.5.3
8052B–AVR–09/08
Normal 8-bit Mode
Clear Timer on Compare Match (CTC) 8-bit Mode
16-bit Mode
In the normal mode, the counter (TCNTnL) is incrementing until it overruns when it passes its
maximum 8-bit value (MAX = 0xFF) and then restarts from the bottom (0x00), see
on page 76
as the TCNTnL becomes zero. The TOVn Flag in this case behaves like a ninth bit, except
that it is only set, not cleared. However, combined with the timer overflow interrupt that auto-
matically clears the TOVn Flag, the timer resolution can be increased by software. There are
no special cases to consider in the Normal 8-bit mode, a new counter value can be written
anytime. The Output Compare Unit can be used to generate interrupts at some given time.
In Clear Timer on Compare or CTC mode, the OCRnA Register is used to manipulate the
counter resolution, see
cleared to zero when the counter value (TCNTn) matches the OCRnA. The OCRnA defines
the top value for the counter, hence also its resolution. This mode allows greater control of the
Compare Match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in
(TCNTn) increases until a Compare Match occurs between TCNTn and OCRnA, and then
counter (TCNTn) is cleared.
Figure 16-3. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using
the OCFnA Flag. If the interrupt is enabled, the interrupt handler routine can be used for
updating the TOP value. However, changing TOP to a value close to BOTTOM when the
counter is running with none or a low prescaler value must be done with care since the CTC
mode does not have the double buffering feature. If the new value written to OCRnA is lower
than the current value of TCNTn, the counter will miss the Compare Match. The counter will
then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the
Compare Match can occur. As for the Normal mode of operation, the TOVn Flag is set in the
same timer clock cycle that the counter counts from MAX to 0x00.
In 16-bit mode, the counter (TCNTnH/L) is a incrementing until it overruns when it passes its
maximum 16-bit value (MAX = 0xFFFF) and then restarts from the bottom (0x0000), see
16-2 on page 76
cycle as the TCNTnH/L becomes zero. The TOVn Flag in this case behaves like a 17th bit,
except that it is only set, not cleared. However, combined with the timer overflow interrupt that
automatically clears the TOVn Flag, the timer resolution can be increased by software. There
TCNTn
Period
for bit settings. The Overflow Flag (TOVn) will be set in the same timer clock cycle
for bit settings. The Overflow Flag (TOVn) will be set in the same timer clock
1
Table 16-2 on page 76
2
3
for bit settings. In CTC mode the counter is
Figure 16-3 on page
4
ATmega4HVD/8HVD
77. The counter value
OCnx Interrupt Flag Set
Table 16-2
Table
77