ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 114

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

21. FET Control
21.1
21.1.1
114
Overview
ATmega4HVD/8HVD
FETs disabled during reset
The FET control is used to enable and disable the Charge FET and Discharge FET. Normally,
the FETs are enabled and disabled by SW writing to the FET Control and Status Register
(FCSR). However, the autonomous Battery Protection circuitry will if necessary override SW
settings to protect the battery cells from too high Charge- or Discharge currents. Note that the
CPU is never allowed to enable a FET that is disabled by the battery protection circuitry. The
FET control is shown in
If Current Protection is activated by the Battery Protection circuitry both the Charge FET and
Discharge FET will be disabled by hardware. When the protection disappears the Current Pro-
tection Timer will ensure a hold-off time of 1 second before software can re-enable the
external FETs.
If C-FET is disabled and D-FET enabled, discharge current will run through the body-drain
diode of the C-FET and vice versa. To avoid the potential heat problem from this situation,
software must ensure that D-FET is not disabled when a charge current is flowing, and that C-
FET is not disabled when a discharge current is flowing.
If charging deeply over-discharged cells, the FET driver must be operated in the Deep Under-
voltage Recovery mode. When the cell voltage raises to an acceptable level, Deep Under-volt-
age Recovery mode should be disabled by software by setting the FCSR (DUVRD bit). To
avoid that C-FET is opened while current protection is active, DUVR mode is automatically
disabled by hardware, in this case.
Figure 21-1. FET Control Block Diagram
During reset, both FETs will be disabled immediately and the chip will exit from DUVR mode. It
is important to notice that a reset will lead to an immediate disabling of the FETs regardless of
the Battery Protection parameter settings. A BOD reset may occur as a result of a short-circuit
condition. Depending on the selected Battery Protection Timing, actual current consumption
and dimensioning of CREG, a BOD reset may occur before the Battery Protection delay timing
has expired, causing the FETs to be disabled.
Power-off Mode
BATTERY_PROTECTION
Figure
21-1.
Register
Control
Status
FET
and
Current Protection
Timer
DUVRD
CFE
DFE
DISCHARGE_EN
CHARGE_EN
DUVR_OFF
8052B–AVR–09/08