ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 76

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

16.5
Table 16-2.
76
Mode
0
1
2
3
4
5
Modes of Operation
ATmega4HVD/8HVD
ICENn
0
0
0
0
1
1
Modes of Operation
TCWn
0
0
1
1
0
1
Figure 16-2. Counter Unit Block Diagram
Signal description (internal signals):
The counter is incremented at each timer clock (clk
restarts from BOTTOM. The counting sequence is determined by the setting of the WGMn0
bits located in the Timer/Counter Control Register (TCCRnA). For more details about counting
sequences, see
external or internal clock source, selected by the Clock Select bits (CSn2:0). When no clock
source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be
accessed by the CPU, regardless of whether clk
(has priority over) all counter clear or count operations. The Timer/Counter Overflow Flag
(TOVn) is set when the counter reaches the maximum value and it can be used for generating
a CPU interrupt.
The mode of operation is defined by the Timer/Counter Width (TCWn), Input Capture Enable
(ICENn) and the Waveform Generation Mode (WGMn0)bits in
Control Register A” on page
Operation.
WGMn0
0
1
0
1
0
0
count
clk
top
Tn
Timer/Counter Mode
Normal 8-bit Mode
8-bit CTC
16-bit Mode
16-bit CTC
8-bit Input Capture
mode
16-bit Input Capture
mode
DATA BUS
”Timer/Counter Timing Diagrams” on page
TCNTn
of Operation
Increment or decrement TCNTn by 1.
Timer/Counter clock, referred to as clk
Signalize that TCNTn has reached maximum value.
86.
Table 16-2 on page 76
count
OCRnB,
OCRnA
0xFFFF
OCRnA
0xFFFF
0xFF
0xFF
TOP
Control Logic
top
Tn
Tn
is present or not. A CPU write overrides
TOVn
(Int.Req.)
clk
) until it passes its TOP value and then
Tn
Update of
Immediate
Immediate
Immediate
Immediate
OCRx at
81. clk
Tn
shows the different Modes of
–
–
in the following.
”TCCRnA – Timer/Counter n
Clock Select
( From Prescaler )
Tn
Detector
Edge
can be generated from an
MAX (0xFFFF)
MAX (0xFFFF)
MAX (0xFFFF)
MAX (0xFF)
MAX (0xFF)
MAX (0xFF)
TOV Flag
Set on
8052B–AVR–09/08
Tn