ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 80

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

16.6.2
16.6.3
16.7
80
Output Compare Unit
ATmega4HVD/8HVD
Noise Canceler
Using the Input Capture Unit
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing
the output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in
Timer/Counter Control Register n B (TCCRnB). When enabled the noise canceler introduces
additional four system clock cycles of delay from a change applied to the input, to the update
of the ICRn Register. The noise canceler uses the system clock and is therefore not affected
by the prescaler.
The noise canceller should only be used for ICP01 (Port PC0).
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICRn Register before the next event occurs, the ICRn will
be overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICRn Register should be read as early in the inter-
rupt handler routine as possible. The maximum interrupt response time is dependent on the
maximum number of clock cycles it takes to handle any of the other interrupt requests.
Measurement of an external signal duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICRn
Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be
cleared by software (writing a logical one to the I/O bit location). For measuring frequency
only, the trigger edge change is not required.
Table 16-3.
Notes:
Table 16-4.
Note:
The comparator continuously compares the Timer/Counter (TCNTn) with the Output Compare
Registers (OCRnA and OCRnB), and whenever the Timer/Counter equals to the Output Com-
pare Regisers, the comparator signals a match. A match will set the Output Compare Flag at
the next timer clock cycle. In 8-bit mode the match can set either the Output Compare Flag
OCFnA or OCFnB, but in 16-bit mode the match can set only the Output Compare Flag
ICS0
ICS1
0
1
0
1
1. See
2. The noise canceller cannot be used with this setting.
1. The noise canceller cannot be used with this setting.
Timer/Counter0 Input Capture Source (ICS)
Timer/Counter1 Input Capture Source (ICS)
Source
ICP00: osi_posedge pin from OSI module
ICP01: Port PC0
”OSI – Oscillator Sampling Interface” on page 27
Source
ICP10: Battery Protection Interrupt
ICP11: Voltage Regulator Interrupt
(1)
(1)
(1) (2)
for details.
8052B–AVR–09/08