ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 59

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

13.2.1
8052B–AVR–09/08
Alternate Functions of Port C
The Port C pins with alternate functions are shown in
Table 13-2.
The alternate pin configuration is as follows:
• INT0/ICP0/XTAL - Port C, Bit 0
INT0, External Interrupt 0: When INT0 is written to one and the I-bit in the Status Register
(SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense
Control bits in the
whether the external interrupt is activated on rising or falling edge or level sensed. Activity on
any of these pins will trigger an interrupt request even if the pin is enabled as an output. This
provides a way of generating a software interrupt.
XTAL, External Clock: When the CKSEL fuse is programmed, PC0 is used as clock source
instead of the Internal RC oscillator (For test purposes only).
• MOSI/INT1/EXT_PROT - Port C, Bit 1
MOSI, Slave Data Input pin for SPI Programming.
INT1, External Interrupt 1: When INT1 is written to one and the I-bit in the Status Register
(SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense
Control bits in the
whether the external interrupt is activated on rising or falling edge or level sensed. Activity on
any of these pins will trigger an interrupt request even if the pin is enabled as an output. This
provides a way of generating a software interrupt.
EXT_PROT, External Protection Input: When the EPID bit in the BPCR Register is cleared,
the External Protection Input functionality is enabled. Note that this port overriding is default
enabled.
Table 13-3
13-3 on page
Table 13-3.
Signal Name
PVOE
PVOV
DIEOE
DIEOV
DI
Port Pin
PC0
PC1
relates the alternate functions of Port C to the overriding signals shown in
58.
Port C Pins Alternate Functions
Overriding Signals for Alternate Functions in PC1:0
”EICRA – External Interrupt Control Register A” on page 53
”EICRA – External Interrupt Control Register A” on page 53
PC1/MOSI/INT1/EXT_PROT
0
0
INT Enable + EPID
1
INT1/EXT_PROT
Alternate Function
INT0/ICP0/XTAL (External Interrupt 0, Timer/Counter 0 input Capture
Trigger or External Clock)
MOSI/INT1/EXT_PROT (SPI BUS Serial Data Input, External Interrupt
1, External Protection Input)
Table
ATmega4HVD/8HVD
PC0/INT0/ICP0/XTAL
0
0
INT Enable + CKSEL
1
INT0/ICP0/XTAL INPUT
13-2.
- defines
- defines
Figure
59