ATMEGA8HVD-4MX Atmel, ATMEGA8HVD-4MX Datasheet - Page 30

• Manufacturer Part Number: ATMEGA8HVD-4MX
• Description: MCU AVR 8K FLASH 2.1-8V 4MHZ QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8HVD-4MX

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 2.4 V
• Data Converters: A/D 1x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 18-MLF® Exposed Pad (Staggered Leads), DFN
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Connectivity: -

8.13.4
30
ATmega4HVD/8HVD
OSICSR – Oscillator Sampling Interface Control and Status Register
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLK-
PCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written.
Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period,
or clear the CLKPCE bit.
• Bit 1:0 – CLKPS1:0: Clock Prescaler Select Bit 1..0
These bits define the division factor between the selected clock source and the internal sys-
tem clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all syn-
chronous peripherals is reduced when a division factor is used. The division factors are given
in
any ongoing ADC conversion.
Table 8-4.
Note:
• Bits 7:5,3:2 – RES: Reserved bits
These bits are reserved bits in the ATmega4HVD/8HVD and will always read as zero.
• Bit 4 - OSISEL0: Oscillator Sampling Interface Select 0
Table 8-5.
• Bit 1 – OSIST: Oscillator Sampling Interface Status
This bit continuously displays the phase of the prescaled clock. This bit can be polled by the
CPU to determine the rising and falling edges of the prescaled clock.
Bit
Read/Write
Initial Value
Table 8-4 on page
1. Reserved values should not be written to CLKPS1..0
CLKPS1
System Clock Prescaler Select
OSISEL Bit Description
0
0
1
1
R
7
–
0
OSISEL0
30. Note that writing to the System Clock Prescaler Select bits will abort
0
1
R
6
–
0
R
5
–
0
OSISEL0
R/W
CLKPS0
4
0
0
1
0
1
R
3
–
0
R
2
–
0
Slow RC Oscillator
Oscillator source
ULP Oscillator
Clock Division Factor
OSIST
R
1
0
Reserved
OSIEN
2
4
8
R/W
0
0
8052B–AVR–09/08
(1)
OSICSR