R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 96

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
12.1
Table 12.2
NOTES:
Count Source
Count Operation
Period
Count Start Condition
Reset Condition of Watchdog
Timer
Count Stop Condition
Operation at the time of
Underflow
The count source of the watchdog timer is the CPU clock when count source protection mode is
disabled. Table 12.2 lists the Specification of Watchdog Timer (When Count Source Protection Mode is
Disabled).
1. The watchdog timer is reset when writing “00h” to the WDTR register before writing “FFh”. The
2. The WDTON bit cannot be changed by a program. When setting the WDTON bit, write “0” to the bit
prescaler is reset after the microcomputer is reset. Some errors occur by the prescaler for the
period of the watchdog timer.
0 of the address 0FFFFh by a flash writer.
When Count Source Protection Mode Disabled
Jan 19, 2006
Item
Specification of Watchdog Timer (When Count Source Protection Mode is Disabled)
Page 81 of 254
CPU clock
Decrement
Division ratio of prescaler(n) x count value of watchdog timer(32768)
n : 16 or 128 (selected by WDC7 bit in WDC register)
e.g.When the CPU clock is 16MHz and prescaler is divided by 16, the
The WDTON bit
of watchdog timer after reset
• When the WDTON bit is set to “1” (watchdog timer is in stop state
• When the WDTON bit is set to “0” (watchdog timer starts
• Reset
• Write “00h” to the WDTR register before writing “FFh”
• Underflow
Stop and wait modes (inherit the count from the held value after exiting
modes)
• When the PM12 bit in the PM1 register is set to “0”
• When the PM12 bit in the PM1 register is set to “1”
The watchdog timer and prescaler stop after reset and the count
starts by writing to the WDTS register
automatically after reset)
The watchdog timer and prescaler start counting automatically after
reset
Watchdog timer reset (refer to 5.5 Watchdog Timer Reset)
after reset)
Watchdog timer interrupt
period is approximately 32.8ms
(2)
in the OFS register (0FFFFh) selects the operation
Specification
CPU clock
12. Watchdog Timer
(1)