R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 169

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
15.3.2
In master receive mode, the master device outputs the receive clock, receives data from the slave
device, and returns an acknowledge signal. Figure 15.12 and Figure 15.13 show the Operation
Timing in Master Receive Mode.
The receive procedure and operation in master receive mode are shown below.
(1) After setting the TEND bit in the ICSR register to “0”, switch from master transmit mode to
(2) When performing the dummy-read of the ICDRR register and starting receive, output the
(3) The 1-frame data receive is completed and the RDRF bit in the ICSR register is set to “1” at
(4) The continuous receive is enabled by reading the ICDRR register every time the RDRF bit is
(5) If the following frame is the last receive frame and the RCVD bit in the ICCR1 register is set to
(6) When the RDRF bit is set to “1” at the rise of the 9th clock of the receive clock, generate the
(7) When the STOP bit in the ICSR register is set to “1”, read the ICDRR register. And set the
(8) Return to slave receive mode.
Jan 19, 2006
Master Receive Operation
master receive mode by setting the TRS bit in the ICCR1 register. And set the TDRE bit in the
ICSR register to “0”.
receive clock synchronizing with the internal clock and receive data. The master device
outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the 9th clock of
the receive clock.
the rise of the 9th clock. At this time, when reading the ICDRR register, the received data can
be read and the RDRF bit is set to “0” simultaneously.
set to “1”. If the 8th clock falls after reading the ICDRR register by the other processes while
the RDRF bit is set to “1”, the SCL signal is fixed “L” until the ICDRR register is read.
“1” (disables the next receive operation) before reading the ICDRR register, the stop condition
generation is enabled after the following receive.
stop condition.
RCVD bit to “0” (maintain the following receive operation).
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15. I
2
C bus interface (IIC)