R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 158

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Figure 15.3
IIC Bus Control Register 1
b7 b6 b5 b4
NOTES :
1.
2.
3.
4.
5.
6.
Set according to the necessary transfer rate in master mode. Refer to Table 15.2 Exam ple of Transfer
Rate for the transfer rate. This bit is used for maintaining of the setup time in transmit mode. The time
is 10Tcyc w hen the CKS3 bit is set to “0” and 20Tcyc w hen the CKS3 bit is set to “1”. (1Tcyc=1/f1(s))
Rew rite the TRS bit betw een the transfer frame.
When the first 7 bits, after the start condition in slave receive mode, match w ith the slave address set in the SAR
register and the 8th bit is set to “1”, the TRS bit is set to “1”.
In master mode w ith the I
and the IIC enters slave receive mode.
When an overrun error occurs in master receive mode of the clock synchronous serial format, the MST bit
is set to “0” and the IIC enters slave receive mode.
Refer to 20.6.1 Access of Registers Associated w ith IIC for the access of registers associated w ith IIC.
Jan 19, 2006
b3 b2
ICCR1 Register
b1
b0
Bit Symbol
Symbol
ICCR1
RCVD
CKS0
CKS1
CKS2
CKS3
TRS
MST
ICE
Page 143 of 254
(6)
2
C bus format, w hen arbitration is lost, the MST and TRS bits are set to “0”
Transmit Clock Select Bit 3 to
0
Transmit / Receive Select
Bit
Master / Slave Select Bit
Receive Disable Bit
IIC Bus Interface Enable Bit
(1)
(2,3)
Address
Bit Name
00B8h
(5)
After reading the ICDRR register w hile the TRS bit
is set to “0”
0 : Maintains the follow ing receive operation
1 : Disables the follow ing receive operation
0 : This module is halted
1 : This module is enabled for transfer
b3 b2 b1 b0
b5 b4
0 0 0 0 : f1/28
0 0 0 1 : f1/40
0 0 1 0 : f1/48
0 0 1 1 : f1/64
0 1 0 0 : f1/80
0 1 0 1 : f1/100
0 1 1 0 : f1/112
0 1 1 1 : f1/128
1 0 0 0 : f1/56
1 0 0 1 : f1/80
1 0 1 0 : f1/96
1 0 1 1 : f1/128
1 1 0 0 : f1/160
1 1 0 1 : f1/200
1 1 1 0 : f1/224
1 1 1 1 : f1/256
0 0 : Slave Receive Mode
0 1 : Slave Transmit Mode
1 0 : Master Receive Mode
1 1 : Master Transmit Mode
(SCL and SDA pins are set to port function)
(SCL and SDA pins are bus drive state)
operations
After Reset
Function
00h
(4)
15. I
2
C bus interface (IIC)
RW
RW
RW
RW
RW
RW
RW
RW
RW