R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 178

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Figure 15.19
15.4.1
In transmit mode, transmit data is output from the SDA pin synchronizing with the fall of the transfer
clock. The transfer clock is output when the MST bit in the ICCR1 register is set to “1” and input when
the MST bit is set to “0”. Figure 15.19 shows the Operating Timing in Transmit Mode (Clock
Synchronous Serial Mode).
The transmit procedure and operation in transmit mode are shown below.
(1) Set the ICE bit in the ICCR1 register to “1” (transfer operation enabled). Set the CKS0 to
(2) The TDRE bit in the ICSR register is set to “1” by selecting transmit mode after setting the TRS
(3) Data is transferred from the ICDRT to ICDRS registers and the TDRE bit is automatically set
ICDRT Register
ICDRS Register
ICCR1 Register
Jan 19, 2006
ICSR Register
by program
TDRE Bit in
Transmit Operation
TRS Bit in
Process
(Output)
CKS3 bits in the ICCR1 register and set the MST bit (initial setting).
bit in the ICCR1 register to “1”.
to “1” by writing transmit data to the ICDRT register after confirming that the TDRE bit is set to
“1”. When writing data to the ICDRT register every time the TDRE bit is set to “1”, the
continuous transmit is enabled. When switching from transmit to receive modes, set the TRS
bit to “0” while the TDRE bit is set to “1”.
SDA
SCL
Operating Timing in Transmit Mode (Clock Synchronous Serial Mode)
(2) Set TRS bit to “1”
“1”
“0”
“1”
“0”
(3) Data write to
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ICDRT register
Data 1
b0
Data 1
1
b1
(3) Data write to
2
ICDRT register
b6
Data 2
7
b7
8
b0
Data 2
1
(3) Data write to
ICDRT register
b6
7
b7
8
15. I
(3) Data write to
Data 3
ICDRT register
2
Data 3
C bus interface (IIC)
b0
1