R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 165

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
15.2
Table 15.3
STIE, NAKIE, RIE, TEIE, TIE : Bits in ICIER register
AL, STOP, NACKF, RDRF, TEND, TDRE : Bits in ICSR register
Transmit Data Empty
Transmit Ends
Receive Data Full
Stop Condition Detection
NACK Detection
Arbitration Lost / Overrun Error
The interrupt request of the IIC contains 6 types when the I
clock synchronous serial format is used. Table 15.3 lists the Interrupt Request of IIC.
Since these interrupt requests are allocated at the IIC interrupt vector table, determining the factor by
each bit is necessary.
When the generation conditions on the Table 15.3 are met, the IIC interrupt request is generated. Set the
interrupt generation conditions to “0” by the IIC interrupt routine. However, the TDRE and TEND bits are
automatically set to “0” by writing transmit data to the ICDRT register and the RDRF bit is automatically
set to “0” by reading the ICDRR register. When writing transmit data to the ICDRT register, the TDRE bit
is set to “0”. When data is transferred from the ICDRT to ICDRS registers, the TDRE bit is set to “1” and
when further setting the TDRE bit to “0”, extra 1 byte may be transmitted.
Interrupt Request
Jan 19, 2006
Interrupt Request
Interrupt Request of IIC
Page 150 of 254
TXI
TEI
RXI
STPI
NAKI
TIE=1 and TDRE=1
TEIE=1 and TEND=1
RIE=1 and RDRF=1
STIE=1 and STOP=1
NAKIE=1 and AL=1 (or
NAKIE=1 and NACKF=1)
Generation Condition
2
C bus format is used and 4 types when the
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
I
2
C bus
15. I
2
Format
C bus interface (IIC)
Enabled
Synchronous
Enabled
Enabled
Disabled
Disabled
Enabled
Clock
Serial