R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 78

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Table 11.3
ILVL2 to ILVL0 Bits
000b
001b
010b
011b
100b
101b
110b
111b
11.1.6.1
11.1.6.2
11.1.6.3
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the
maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.
The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is acknowledged and the CPU branches to the corresponding interrupt vector, the
IR bit is set to “0” (interrupt not requested).
The IR bit can be set to “0” by a program. Do not write “1” to this bit.
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 11.3 lists the Settings of Interrupt Priority Levels and Table 11.4 lists the Interrupt Priority
Levels Enabled by IPL.
The following are conditions under which an interrupt is acknowledged:
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. They do not affect one
another.
•
•
•
Jan 19, 2006
I flag = 1
IR bit = 1
interrupt priority level > IPL
Settings of Interrupt Priority
Levels
IR Bit
ILVL2 to ILVL0 Bits and IPL
I Flag
Level 0 (interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Interrupt Priority Level
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Priority Order
High
Low
−
Table 11.4
000b
001b
010b
011b
100b
101b
110b
111b
IPL
IPL
Interrupt Priority Levels Enabled by
Interrupt level 1 and above
Interrupt level 2 and above
Interrupt level 3 and above
Interrupt level 4 and above
Interrupt level 5 and above
Interrupt level 6 and above
Interrupt level 7 and above
Disables all maskable interrupts
Enabled Interrupt Priority Levels
11. Interrupt