R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 39

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
5.3
5.4
5.5
5.6
A reset is applied using the built-in voltage detection 1 circuit. The voltage detection 1 circuit monitors
the input voltage to the VCC pin. The voltage to monitor is Vdet1.
When the input voltage to the VCC pin reaches to the Vdet1 level or below, the pins, CPU and SFR are
reset.
And when the input voltage to the VCC pin reaches to the Vdet1 level or above, count operation of the
low-speed on-chip oscillator clock starts. When the operation counts the low-speed on-chip oscillator
clock for 32 times, the internal reset signal is held “H” and the microcomputer enters the reset sequence
(See Figure 5.3). The low-speed on-chip oscillator clock divide-by-8 is automatically selected for the
CPU after reset.
Refer to 4. Special Function Register (SFR) for the status of the SFR after voltage monitor 1 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches to the Vdet1 level or
below during writing to the internal RAM, the internal RAM is in indeterminate state.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 1 reset.
A reset is applied using the built-in voltage detection 2 circuit. The voltage detection 2 circuit monitors
the input voltage to the VCC pin. The voltage to monitor is Vdet2.
When the input voltage to the VCC pin drops to the Vdet2 level or below, the pins, CPU and SFR are
reset and the program is executed beginning with the address indicated by the reset vector. After reset,
the low-speed on-chip oscillator clock divide-by-8 is automatically selected for the CPU clock.
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Register (SFR) for
details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches to the Vdet2 level or
below during writing to the internal RAM, the internal RAM is in indeterminate state.
Refer to 6. Voltage Detection Circuit for details of voltage monitor 2 reset.
When the PM12 bit in the PM1 register is set to “1” (reset when watchdog timer underflows), the
microcomputer resets its pins, CPU and SFR if the watchdog timer underflows. Then the program is
executed beginning with the address indicated by the reset vector. After reset, the low-speed on-chip
oscillator clock divide-by-8 is automatically selected for the CPU clock.
After reset, the low-speed on-chip oscillator clock divide-by-8 is automatically selected for the CPU
clock.
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Register (SFR) for
details.
The internal RAM is not reset. When the watchdog timer underflows, the internal RAM is in
indeterminate state.
Refer to 12. Watchdog Timer for watchdog timer.
When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer resets its
pins, CPU and SFR. The the program is executed beginning with the address indicated by the reset
vector. After reset, the low-speed on-chip oscillator clock divide-by-8 is automatically selected for the
CPU clock.
The software reset does not reset some SFRs. Refer to 4. Special Function Register (SFR) for details.
The internal RAM is not reset.
Voltage Monitor 1 Reset
Voltage Monitor 2 Reset
Watchdog Timer Reset
Software Reset
Jan 19, 2006
Page 24 of 254
5. Reset