R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 162

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Figure 15.7
IIC Bus Status Register
b7 b6 b5 b4
NOTES :
1.
2.
3.
4.
5.
6.
7.
Each bit is set to “0” when reading “1” bef ore writing “0”.
This f lag is enabled in slav e receiv e mode of the I
When two or more master dev ices attempt to occupy the bus at nearly the same time, if the IIC monitors the SDA pin and the data
which the IIC transmits is dif f erent, the AL f lag is set to “1” and the bus is occupied by the other masters.
The NACKF bit is enabled when the ACKE bit in the ICIER register is set to “1” (when the receiv e acknowledge bit is set to “1”,
transf er is halted)
The RDRF bit is set to “0” when reading data f rom the ICDRR register.
The TEND and TDRE bits are set to “0” when writing data to the ICDRT register.
Ref er to 20.6.1 Access of Registers Associated with IIC f or the access of registers associated with IIC.
Jan 19, 2006
b3
b2 b1
ICSR Register
b0
Bit Symbol
Symbol
NACKF
STOP
RDRF
TEND
TDRE
ICSR
ADZ
AAS
(7)
Page 147 of 254
AL
General Call Address
Recognition Flag
Slave Address
Recognition Flag
Arbitration Lost Flag /
Overrun Error Flag
Stop Condition
Detection Flag
No Acknow ledge
Detection Flag
Receive Data Register
Full
Transmit End
Transmit Data Empty
(1,5)
Address
Bit Name
00BCh
(1,6)
(1)
(1,4)
2
C bus f ormat.
(1,2)
(1)
(1)
(1,6)
When detecting the general call address, this f lag is set to “1”.
This f lag is set to “1” when the f irst f rame f ollowing start
condition matches the SVA0 to SVA6 bits in the SAR register in
slav e receiv e mode. (Detect the slav e address and generate call
address)
When the I2C bus f ormat is used, this f lag indicates that
arbitration is lost in master mode. In the f ollowing case, this f lag
is set to “1”
• When the internal SDA signal and SDA pin lev el do not
• When the start condition is detected and the SDA pin is
This f lag indicates that an ov errun error occurs when the clock
sy nchronous f ormat is used.
In the f ollowing case, this f lag is set to “1”.
• When the last bit of the f ollowing data is receiv ed while
In the f ollowing cases, this f lag is set to “1”:
• When the stop condition is detected af ter the f rame is
• When the stop condition is detected af ter the address set
• When the stop condition is detected af ter detecting the
When no ACKnowledge is detected f rom receiv e dev ice when
transmit, this f lag is set to “1”
When receiv e data is transf erred f rom ICDRS to ICDRR
registers, this f lag is set to “1”
When the 9th clock of the SCL signal with the I2C bus f ormat
while the TDRE bit is set to “1”, this f lag is set to “1”
This f lag is set to “1” when the f inal bit of the transmit f rame is
transmitted with the clock sy nchronous f ormat
In the f ollowing cases, this f lag is set to “1”:
• Data is transf erred f rom ICDRT to ICDRS
• When setting the TRS bit in the ICCR1
• When generating the start condition
• When changing f rom slav e receiv e mode to
match at the rise of the SCL signal in master transmit
mode
held “H” in master transmit / receiv e mode
the RDRF bit is set to “1”
transf erred in master mode.
in the SAR register matches with the 1st-by te slav e
address af ter detecting the start condition in slav e mode.
general call address in slav e mode.
registers and ICDRT register is empty
register to “1” (transmit mode)
(including retransmit)
slav e transmit mode
(3)
.
After Reset
Function
00h
15. I
2
C bus interface (IIC)
RW
RW
RW
RW
RW
RW
RW
RW
RW