R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 150

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
14.2
Table 14.4
NOTES:
Transfer Data Format
Transfer Clock
Transmit Start Condition
Receive Start Condition
Interrupt Request
Generation Timing
Error Detection
The UART mode allows transmit and receive data after setting the desired bit rate and transfer data
format. Table 14.4 lists the Specification of UART Mode. Table 14.5 lists the Registers to Be Used and
Settings in UART Mode.
1. If an overrun error occurs, the value in the U0RB register will be indeterminate. The IR bit in the
S0RIC register remains unchanged.
Clock Asynchronous Serial I/O (UART) Mode
Jan 19, 2006
Item
Specification of UART Mode
Page 135 of 254
• Character bit (transfer data): selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: selectable from odd, even, or none
• Stop bit: selectable from 1 or 2 bits
• CKDIR bit in U0MR register is set to “0” (internal clock) : fj/(16(n+1))
• CKDIR bit is set to “1” (external clock) : fEXT/(16(n+1))
• Before transmit starts, the following are required
• Before receive starts, the following are required
• When transmitting, one of the following conditions can be selected
• When receiving
• Overrun error
• Framing error
• Parity error
• Error sum flag
fj=f1, f8, f32 n=setting value in U0BRG register: 00h to FFh
fEXT: input from CLK0 pin n=setting value in U0BRG register: 00h to FFh
- TE bit in U0C1 register is set to “1” (transmit enabled)
- TI bit in U0C1 register is set to “0” (data in U0TB register)
- RE bit in U0C1 register is set to “1” (receive enabled)
- Detects start bit
- U0IRS bit is set to “0” (transmit buffer empty):
- U0IRS bit is set to “1” (transfer ends):
When transferring data from the UART0 receive register to U0RB register
(when receive ends)
This error occurs if serial interface starts receiving the following data
before reading the U0RB register and receiving the bit one before the last
stop bit of the following data
This error occurs when the number of stop bits set are not detected
This error occurs when parity is enabled, the number of 1’s in parity and
character bits do not match the number of 1’s set
This flag is set is set to “1” when any of the overrun, framing, and parity
errors is generated
when transferring data from the U0TB register to UART0 transmit
register (when transmit starts)
when serial interface completes transmitting data from the UART0
transmit register
(1)
Specification
14. Serial Interface