R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 228
![IC R8C MCU FLASH 8K 20SSOP](/photos/12/35/123577/r5f21162sp_u0_sml.jpg)
R5F21162SP#U0
Manufacturer Part Number
R5F21162SP#U0
Description
IC R8C MCU FLASH 8K 20SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/16r
Datasheets
1.R5F211A2SPU0.pdf
(300 pages)
2.R5F21173DSPU0.pdf
(40 pages)
3.R5F21173DSPU0.pdf
(281 pages)
Specifications of R5F21162SP#U0
Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SIO, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-SSOP
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
18.4.5
Table 18.6
NOTES:
1
1
0
FMR07(SR5) FMR06(SR4)
1. The microcomputer enters read array mode by writing “FFh” in the second bus cycle of these
FRM00 Register (Status
When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating
occurrence of each specific error. Therefore, Checking these status bits (full status check) can
determine the executed result.
Table 18.6 lists the Errors and FMR0 Register Status. Figure 18.14 shows the Full Status Check and
Handling Procedure for Each Error.
commands, at the same time the command code written in the first bus cycle will disabled.
Register) Status
Jan 19, 2006
Full Status Check
Errors and FMR0 Register Status
1
0
1
Page 213 of 254
Command
Sequence
Error
Erase Error
Program Error • When the program command is executed but not
Error
• When any command is not written correctly
• When invalid data other than those that can be written in
• When executing the program command or block erase
• When inputting and erasing the address in which the
• When executing to erase the block which disables
• When inputting and writing the address in which the
• When executing to write the block which disables
• When the block erase command is executed but not
the second bus cycle of the block erase command is
written (i.e., other than “D0h” or “FFh”)
command while rewriting is disabled using the FMR02
bit in the FMR0 register, the FMR15 or FMR16 bit in the
FMR1 register.
Flash memory is not allocated during the erase
command input
rewriting during the erase command input.
Flash memory is not allocated during the write command
input.
rewriting during the write command input.
automatically erased correctly
automatically programmed correctly.
Error Occurrence Condition
18. Flash Memory Version
(1)
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