R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 215

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
18.4
Table 18.3
NOTES:
Operating Mode
Area in which rewrite
control program can be
allocated
Area in which rewrite
control program can be
executed
Area which can be
rewritten
Software Command
Restriction
Mode after Program or
Erase
CPU Status during
Auto-Write and Auto-Erase
Flash Memory Status
Detection
Condition for Transition to
Erase-Suspend
CPU Clock
In CPU rewrite mode, user ROM area can be rewritten by executing software commands from the CPU.
Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on a board
without using such as a ROM programmer. Execute the program and block erase commands only to
each block in user ROM area.
When an interrupt request is generated during an erase operation in CPU rewrite mode, the flash
module contains an erase-suspend function which performs the interrupt process after the erase
operation is halted temporarily. During the erase-suspend, user ROM area can be read by a program.
CPU rewrite mode contains erase write 0 mode(EW0 mode) and erase write 1 mode(EW1 mode). Table
18.3 lists the Differences between EW0 Mode and EW1 Mode.
1. When setting the FMR02 bit in the FMR0 register to “1” (rewrite enables) and rewriting Block 0 is
enabled by setting the FMR15 bit in the FMR1 register to “0” (rewrite enables). Rewriting Block 1 is
enabled by setting the FMR16 bit to “0” (rewrite enables).
CPU Rewrite Mode
Jan 19, 2006
Item
Differences between EW0 Mode and EW1 Mode
Page 200 of 254
Single chip mode
User ROM area
Necessary to transfer to any areas
other than the flash memory (e.g.,
RAM) before executing
User ROM area
None
Read status register mode
Operation
• Read the FMR00, FMR06, and
• Execute the read status register
Set the FMR40 and FMR41 bits in
the FMR4 register to “1” by a
program.
5MHz or below
FMR07 bits in the FMR0 register by
a program
command and read the SR7, SR5,
and SR4 bits in the status register.
EW0 Mode
Single chip mode
User ROM area
Executing directly on user ROM area
is possible
User ROM area
• Program, block erase command
• Disables to execute the read status
Read array mode
Hold state (I/O ports hold state
before the command is executed)
Read the FMR00, FMR06, and
FMR07 bits in the FMR0 register by a
program
The FMR40 bit in the FMR4 register
is set to “1” and the interrupt request
of the enabled maskable interrupt is
generated
No restriction to the following (clock
frequency to be used)
Disable to execute on any block
which contains a rewrite control
program
register command
However, other than the blocks
which contain a rewrite control
program
(1)
EW1 Mode
18. Flash Memory Version