R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 183

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Figure 15.24
NOTES:
1. Do not generate the interrupt during the process of step (1) to (3).
2. When receiving 1 byte, skip step (2) to (6) after (1) and jump to process of step (7).
Jan 19, 2006
Process of step (8) is dummy-read in the ICDRR register.
ICSR Register
ICCR1 Register
ICSR Register
ICIER Register
ICIER Register
ICCR1 Register
ICSR Register
ICCR2 Register
ICCR1 Register
ICCR1 Register
Example of Register Setting in Master Receive Mode
Read RDRF bit in ICSR register
Read RDRF bit in ICSR register
Read STOP bit in ICSR register
Dummy-read in ICDRR register
No
No
No
Master Receive Mode
Read ICDRR register
Read ICDRR register
Read ICDRR register
Yes
Yes
Yes
Last receive
RDRF=1 ?
RDRF=1 ?
STOP=1 ?
Page 168 of 254
ACKBT Bit ← 0
ACKBT Bit ← 1
- 1 ?
End
TEND Bit ← 0
TDRE Bit ← 0
RCVD Bit ← 1
BBSY Bit ← 0
STOP Bit ← 0
RCVD Bit ← 0
TRS Bit ← 0
SCP Bit ← 0
MST Bit ← 0
No
Yes
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(1) Set the TEND bit to “0” and set to master transmit mode.
(2) Set the ACKBT bit to the transmit device
(3) Dummy-read to the ICDRR register
(4) Wait for 1 byte to be received
(5) Judge (last receive - 1)
(6) Read the receive data
(7) Set the ACKBT bit of the last byte and set to disable the
(8) Read the receive data of (last byte - 1)
(9) Wait the last byte is received
(10) Set the STOP bit to “0”
(11) Generate the stop condition
(12) Wait the stop condition is generated
(13) Read the receive data of the last byte
(14) Set the RCVD bit to “0”
(15) Set to slave receive mode
continuous receive (RCVD=1)
Set the TDRE bit to “0”
(1,2)
(2)
(1)
15. I
(1)
2
C bus interface (IIC)