R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 81

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Figure 11.7
Figure 11.8
A d d re s s
11.1.6.7
m − 4
m − 3
m − 2
m − 1
m + 1
m
S ta ck sta te b e fo re in te rru p t re q u e s t
is a c kn o w le d g e d
In the interrupt sequence, the FLG register and PC are saved to the stack.
After 4 high-order bits in the PC and 4 high-order (IPL) and 8 low-order bits in the FLG register,
extended to 16 bits, are saved to the stack, the 16 low-order bits in the PC are saved. Figure 11.7
shows the Stack State Before and After Acknowledgement of Interrupt Request.
The other necessary registers are saved by a program at the beginning of the interrupt routine. The
PUSHM instruction can save several registers in the register bank being currently used
instruction.
NOTES:
The register saving operation which is performed in the interrupt sequence is saved in 8 bits every 4
steps. Figure 11.8 shows Operation of Saving Register.
M S B
C o n te n t o f P re vio u s S ta ck
C o n te n t o f P re vio u s S ta ck
Jan 19, 2006
1. Selectable from the R0, R1, R2, R3, A0, A1, SB and FB registers.
Address
NOTES :
[SP]−5
[SP]−4
[SP]−3
[SP]−2
[SP]−1
1. [SP] indicates the default value of the SP when interrupt request is acknowledged.
[SP]
software number 32 to 63 INT instructions, this SP is specified by the U
flag. Otherwise it is ISP.
Saving a Register
S ta ck
After registers are saved, the SP content is [SP] minus 4.
Stack State Before and After Acknowledgement of Interrupt Request
Operation of Saving Register
N O T E S
1 .W h e n e xe c u tin g th e so ftw a re n u m b e r 3 2 to 6 3 IN T in stru ctio n s,
th is S P is s p e cifie d b y th e U fla g . O th e rw is e it is IS P .
FLGH
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L S B
Stack
PCM
FLGL
PCL
[S P ]
S P v a lu e b e fo re
in te rru p t re q u e s t is
a c k n o w le d g e d
PCH
Sequence in which
order registers are
saved
completed saving
registers in four
operations.
(3)
(4)
(1)
(2)
Saved, 8 bits at a time
A d d re ss
m − 4
m − 3
m − 2
m − 1
m
m + 1
S ta c k s ta te a fte r in te rru p t re q u e st
is a ck n o w le d g e d
When executing the
M S B
C o n te n t o f P re vio u s S ta ck
C o n te n t o f P re vio u s S ta ck
F L G H
F L G L
P C M
P C L
S ta c k
PCH
PCM
PCL
FLGH
FLGL
P C H
: High-order 4 bits of PC
: Middle-order 8 bits of PC
: Low-order 8 bits of PC
: High-order 4 bits of FLG
: Low-order 8 bits of FLG
L S B
P C H
P C M
P C L
F L G H
F L G L
[S P ]
N e w S P V a lu e
: H ig h -o rd e r 4 b its o f P C
: M id d le -o rd e r 8 b its o f P C
: L o w -o rd e r 8 b its o f P C
: H ig h -o rd e r 4 b its o f F L G
: L o w -o rd e r 8 b its o f F L G
(1)
11. Interrupt
with 1