R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 93

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
12. Watchdog Timer
The watchdog timer is a function to detect when the program is out of control. To use the watchdog timer is
recommend for improving reliability of a system. The watchdog timer contains a 15-bit counter and can
select count source protection mode is enabled or disabled. Table 12.1 lists the Count Source Protection
Mode is Enabled / Disabled.
Refer to 5.5 Watchdog Timer Reset for details of the watchdog timer reset.
Figure 12.1 shows the Block Diagram of Watchdog Timer and Figures 12.2 to 12.3 show the OFS, WDC,
WDTR, WDTS and CSPR Registers.
Figure 12.1
Table 12.1
Count Source
Count Operation
Reset Condition of Watchdog
Timer
Count Start Condition
Count Stop Condition
Operation at the time of
Underflow
CPU Clock
NOTES:
Jan 19, 2006
1. When the CSPRO bit is set to “1” (count source protection mode enabled), “0FFFh” is set.
Reset Signal
Write to WDTR register
Count Source Protection Mode is Enabled / Disabled
Block Diagram of Watchdog Timer
Item
Internal
Page 78 of 254
Prescaler
1/128
1/16
CPU clock
Decrement
• Reset
• Write “00h” to the WDTR register before writing “FFh”
• Underflow
Either of following can be selected
• After reset, count starts automatically
• Count starts by writing to WDTS register
Stop mode, wait mode
Watchdog timer interrupt or
watchdog timer reset
When Count Source Protection
WDC7=1
WDC7=0
fRING-S
Mode is Disabled
CSPRO=0
CSPRO=1
Watchdog Timer
Low-speed on-chip oscillator
clock
None
Watchdog timer reset
When Count Source Protection
Set to
“7FFFh”
Mode is Enabled
CSPRO : Bit in CSPR register
WDC7 : Bit in WDC register
(1)
12. Watchdog Timer
PM12=0
Watchdog Timer
Interrupt Request
PM12=1
Watchdog
Timer Reset