R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 172

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
15.3.3
In slave transmit mode, the slave device outputs the transmit data while the master device outputs
the receive clock and returns an acknowledge signal. Figure 15.14 and Figure 15.15 show the
Operation Timing in Slave Transmit Mode.
The transmit procedure and operation in slave transmit mode are shown below.
(1) Set the ICE bit in the ICCR1 register to “1” (transfer operation enabled). Set the WAIT and
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave
(3) When the TDRE bit in the ICDRT register is set to “1” after writing the last transmit data to the
(4) The SCL signal is released by setting the TRS bit to “0” and performing the dummy-read of the
(5) Set the TDRE bit to “0”.
Jan 19, 2006
Slave Transmit Operation
MLS bits in the ICMR register and CKS0 to CKS3 bits in the ICCR1 register (initial setting). Set
the TRS and MST bits in the ICCR1 register to “0” and wait until the slave address matches in
slave receive mode.
device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of
the 9th clock. At this time, if the 8-bit data (R/W) is set to “1”, the TRS and TDRE bit in the
ICSR register are set to “1”, the mode is switched to slave transmit mode automatically. When
writing transmit data to the ICDRT register every time the TDRE bit is set to “1”, the continuous
transmit is enabled.
ICDRT register, wait until the TEND bit in the ICSR register is set to “1” while the TDRE bit is
set to “1”. When the TEND bit is set to “1”, set the TEND bit to “0”.
ICDRR register for the end process.
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15. I
2
C bus interface (IIC)