R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 277

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
2.00
REVISION HISTORY
Jan 12, 2006
Date
173, 176,
183, 184 Figure 17.1 Configuration of Programmable I/O Ports (1),
202, 203 18.4.2.1 FMR00 Bit to 18.4.2.12 FMR46 bit revised
179 to
189 to
Page
127
128
136
147
172
178
181
185
187
188
192
194
196
197
199
203
204
205
206
211
214
Figure 14.3 U0TB, U0RB and U0BRG Registers;
Figure 14.4 U0MR and U0C0 Registers;
Table 14.5 Registers to Be Used and Settings in UART Mode;
Figure 15.7 ICSR Register revised
Figure 16.1 Block Diagram of A/D Converter “Vref“ → “Vcom” revised
Figure 16.2 ADCON0 and ADCON1 Registers,
Figure 16.4 ADCON0 and ADCON1 Registers in One-Shot Mode,
Figure 16.5 ADCON0 and ADCON1 Registers in Repeat Mode;
Figure 16.6 Timing Diagram of A/D Conversion revised and
16.4 A/D Conversion Cycles to 16.6 Inflow Current Bypass Circuit added
Figure 17.2 Configuration of Programmable I/O Ports (2); NOTE1 added
Figure 17.3 Configuration of Programmable I/O Ports (3) NOTE4 added
Figure 17.5 PD1, PD3 and PD4 Registers,
Figure 17.6 P1, P3 and P4 Registers; NOTE1, 2 revised
Figure 17.7 PUR0 and PUR1 Registers revised
17.4 Port setting added, Table 17.4 Port P1_0/KI0/AN8/CMP0_0 Setting
to Table 17.17 Port P4_5/INT0 Setting added
Table 18.1 Flash Memory Version Performance;
18.2 Memory Map;
Figure 18.1 Flash Memory Block Diagram for R8C/16 Group revised
Figure 18.2 Flash Memory Block Diagram for R8C/17 Group revised
Figure 18.4 OFS Register; NOTE1 revised, NOTE2 added
Figure 18.5 FMR0 Register; NOTE6 added
Figure 18.6 FMR1 and FMR4 Registers; FMR4 Register NOTE2 revised
Figure 18.7 Timing on Suspend Operation added
Figure 18.8 How to Set and Exit EW0 Mode and Figure 18.9 How to Set
and Exit EW1 Mode revised
Figure 18.13 Block Erase Command (When Using Erase-Suspend
Function) revised
Figure 18.14 Full Status Check and Handling Procedure for Each Error
revised
U0TB and U0RB Registers revised, U0BRG register NOTE3 added
U0C0 register NOTE1 added
U0BRG: “ − “ → “0 to 7” revised
Program and Erase Endurance: (Program area) → (Program ROM),
“The user ROM ... area ... Block A and B.” →
“The user ROM ... area (program ROM) ... Block A and B (data flash).”
revised
ADCON0 Register revised
R8C/16 Group, R8C/17 Group Hardware
C - 8
Description
Summary
(Data area) → (Data flash) revised