R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 179

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Figure 15.20
15.4.2
In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when the
MST bit in the ICCR1 register is set to “1” and input when the MST bit is set to “0”.
Figure 15.20 shows the Operating Timing in Receive Mode (Clock Synchronous Serial Mode).
The receive procedure and operation in receive mode are shown below.
ICDRR Register
(1) Set the ICE bit in the ICCR1 register to “1” (transfer operation enabled). Set the CKS0 to
(2) The output of the receive clock stars by setting the MST bit to “1” when the transfer clock is
(3) Data is transferred from the ICDRS to ICDRR registers and the RDRF bit in the ICSR register
(4) When the MST bit is set to “1”, set the RCVD bit in the ICCR1 register to “1” (disables the
ICDRS Register
Jan 19, 2006
ICSR Register
by program
RDRF Bit in
Receive Operation
MST Bit in
TRS Bit in
Process
CKS3 bits in the ICCR1 register and set the MST bit (initial setting).
output.
is set to “1”, when the receive is completed. Since the following-byte data is enabled to receive
when the MST bit is set to “1”, the continuous clock is output. The continuous receive is
enabled by reading the ICDRR register every time the RDRF bit is set to “1”. An overrun is
detected at the rise of the 8th clock while the RDRF bit is set to “1”, the AL bit in the ICSR
register is set to “1”. At this time, the former receive data is retained in the ICDRR register.
following receive operation) and read the ICDRR register. The SCL signal is fixed “H” after the
receive of the following-byte data is completed.
(Input)
ICCR1
ICCR1
SDA
SCL
Operating Timing in Receive Mode (Clock Synchronous Serial Mode)
“1”
“0”
“1”
“0”
“1”
“0”
(2) Set MST bit to “1”
(When transfer clock is output)
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b0
1
b1
Data 1
2
(3) Read ICDRR register
b6
7
b7
8
b0
Data 1
1
Data 2
b6
7
(3) Read ICDRR register
b7
8
15. I
Data 2
1
2
C bus interface (IIC)
b0
Data 3
2