R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 80

IC R8C MCU FLASH 8K 20SSOP

R5F21162SP#U0

Manufacturer Part Number
R5F21162SP#U0
Description
IC R8C MCU FLASH 8K 20SSOP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/R8C/Tiny/16r
Datasheets

Specifications of R5F21162SP#U0

Core Processor
R8C
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SIO, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
13
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
20-SSOP
For Use With
R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Figure 11.6
Table 11.5
Watchdog Timer, Oscillation Stop Detection, Voltage Monitor 2 7
Software, Address Match, Single-Step
11.1.6.5
11.1.6.6
Figure 11.6 shows an Interrupt Response Time. The interrupt response time is the period between
an interrupt request generation and the execution of the first instruction in an interrupt routine. An
interrupt response time includes the period between an interrupt request generation and the
completed execution of an instruction (see #a in Figure 11.6) and the period required to perform an
interrupt sequence (20 cycles, see #b in Figure 11.6).
When an interrupt request of a maskable interrupt is acknowledged, the interrupt priority level of the
acknowledged interrupt is set in the IPL.
When a software interrupt and special interrupt request are acknowledged, the value listed in Table
11.5 is set to the IPL. Table 11.5 lists the IPL Value When Software or Special Interrupts Is
Acknowledged.
Jan 19, 2006
Interrupt request is generated Interrupt request is acknowledged
Interrupt Response Time
IPL Change when Interrupt Request is Acknowledged
IPL Value When Software or Special Interrupts Is Acknowledged
Interrupt Response Time
(a) Period between an interrupt request generation and the completed execution of an
(b) 21 cycles for address match and single-step interrupts.
instruction. The length of this time varies depending on the instruction being executed.
The DIVX instruction requires the longest time; 30 cycles (no wait and when the register
is set as the divisor)
Interrupt Factor
Page 65 of 254
Instruction
(a)
Interrupt Response Time
Interrupt Sequence
20 Cycles (b)
Not changed
interrupt routine
Instruction in
Value Set to IPL
Time
11. Interrupt

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