R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 167

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
15.3.1
In master transmit mode, the master device outputs the transmit clock and data, and the slave device
returns an acknowledge signal. Figure 15.10 and Figure 15.11 show the Operation Timing in Master
Transmit Mode.
The transmit procedure and operation in master transmit mode are shown below.
(1) Set the ICE bit in the ICCR1 register to “1” (transfer operation enabled). Set the WAIT and
(2) Read the BBSY bit in the ICCR2 register to confirm that the bus is free. Set the TRS and MST
(3) After confirming that the TDRE bit in the ICSR register is set to “1” (data is transferred from the
(4) When the transmit of 1-byte data is completed while the TDRE bit is set to “1”, the TEND bit in
(5) Write the transmit data after the 2nd byte to the ICDRT register every time the TDRE bit is set
(6) When writing the number of bytes to be transmitted to the ICDRT register, wait until the TEND
(7) When the STOP bit in the ICSR register is set to “1”, return to slave receive mode.
Jan 19, 2006
Master Transmit Operation
MLS bits in the ICMR register and set the CKS0 to CKS3 bits in the ICCR1 register (initial
setting).
bits in the ICCR1 register to master transmit mode. The start condition is generated by writing
“1” to the BBSY bit and “0” to the SCP bit by the MOV instruction.
ICDRT to ICDRS registers), write transmit data to the ICDRT register (data in which a slave
address and R/W are shown at the 1st byte). At this time, the TDRE bit is automatically set to
“0” and data is transferred from the ICDRT to ICDRS registers, the TDRE bit is set to “1” again.
the ICSR register is set to “1” at the rise of the 9th transmit clock pulse. Read the ACKBR bit in
the ICIER register, and confirm that the slave is selected. Write the 2nd-byte data to the
ICDRT register. Since the slave device is not acknowledged when the ACKBR bit is set to “1”,
generate the stop condition. The stop condition is generated by the writing “0” to the BBSY bit
and “0” to the SCP bit by the MOV instruction. The SCL signal is held “L” until data is available
and the stop condition is generated.
to “1”.
bit is set to “1” while the TDRE bit is set to “1”. Or wait for NACK (the NACKF bit in the ICSR
register is set to “1”) from the receive device while the ACKE bit in the ICIER register is set to
“1” (when the receive acknowledge bit is set to “1”, transfer is halted). And generate the stop
condition before setting the TEND and NACKF bits to “0”.
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15. I
2
C bus interface (IIC)