R5F21162SP#U0 Renesas Electronics America, R5F21162SP#U0 Datasheet - Page 214

• Manufacturer Part Number: R5F21162SP#U0
• Description: IC R8C MCU FLASH 8K 20SSOP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/R8C/Tiny/16r

Specifications of R5F21162SP#U0

• Core Processor: R8C
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SIO, UART/USART
• Peripherals: LED, POR, Voltage Detect, WDT
• Number Of I /o: 13
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 20-SSOP
• For Use With: R0K521134S000BE - KIT EVAL STARTER FOR R8C/13
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/16 Group, R8C/17 Group
Rev.2.10
REJ09B0169-0210
Figure 18.4
18.3.2
Option Function Select Register
b7 b6 b5 b4
NOTES :
1.
2. If the block including the OFS register is erased, “FFh” is set to the OFS register.
1 1 1
The ROM code protect function disables to read and change the internal flash memory by the OFS
register in parallel I/O mode. Figure 18.4 shows the OFS Register.
The ROM code protect function is enabled by writing “0” to the ROMCP1 bit and “1” to the ROMCR bit
and disables to read and change the internal flash memory. Once the ROM code protect is enabled,
the content in the internal flash memory cannot be rewritten in parallel I/O mode. To disable ROM
code protect, erase the block including the OFS register with CPU rewrite mode or standard serial I/O
mode.
The OFS register is on the flash memory. Write to the OFS register w ith a program.
Jan 19, 2006
ROM Code Protect Function
b3 b2 b1 b0
OFS Register
1
Bit Symbol
CSPROINI
ROMCP1
WDTON
ROMCR
(b6-b4)
Symbol
OFS
(b1)
Page 199 of 254
—
—
Watchdog Timer Start
Select Bit
Reserved Bit
ROM Code Protect
Disabled Bit
ROM Code Protect Bit
Reserved Bit
Count Source Protect
Mode After Reset Select
Bit
(1)
Address
Bit Name
0FFFFh
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Set to “1”
0 : ROM code protect disabled
1 : ROMCP1enabled
0 : ROM code protect enabled
1 : ROM code protect disabled
Set to “1”
0 : Count source protect mode after reset enabled
1 : Count source protect mode after reset disabled
Before Shipment
Function
FFh
(2)
18. Flash Memory Version
RW
RW
RW
RW
RW
RW
RW