DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 621
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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22.10
There are three modes, high-speed, medium-speed, and sub-active, in which the CPU executes
programs. When a direct transition is made, there is no interruption of program execution when
shifting between high-speed and sub-active modes. Direct transitions are enabled by setting the
LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct
transition interrupt exception processing starts.
22.10.1 Direct Transitions from High-Speed Mode to Sub-Active Mode
Execute the SLEEP instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR
LSON bit = 1, and DTON bit = 1, and TSCR_1 (WDT_1) PSS bit = 1 to make a transition to sub-
active mode.
22.10.2 Direct Transitions from Sub-Active Mode to High-Speed Mode
Execute the SLEEP instruction in sub-active mode when the SBYCR SSBY bit = 1, LPWRCR
LSON bit = 0, and DTON bit = 1, and TSCR_1 (WDT_1) PSS bit = 1 to make a direct transition
to high-speed mode after the time set in SBYCR STS2 to STS0 has elapsed.
22.11
22.11.1 I/O Port Status
In software standby mode and watch mode, I/O port states are retained. Therefore, there is no
reduction in current dissipation for the output current when a high-level signal is output.
22.11.2 Current Dissipation during Oscillation Settling Wait Period
Current dissipation increases during the oscillation settling wait period.
22.11.3 DTC Module Stop (Supported Only by the H8S/2268 Group)
Depending on the operating status of the DTC, the MSTPA6 bit may not be set to 1. Setting of the
DTC module stop mode should be carried out only when the respective module is not activated.
For details, refer to section 8, Data Transfer Controller (DTC).
Direct Transitions
Usage Notes
Rev. 5.00 Sep. 01, 2009 Page 569 of 656
Section 22 Power-Down Modes
REJ09B0071-0500
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