DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 620
![IC H8S/2266 MCU FLASH 100-TQFP](/photos/12/29/122926/df2266tf13v_sml.jpg)
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 620 of 712
- Download datasheet (5Mb)
Section 22 Power-Down Modes
22.9
22.9.1
When the SLEEP instruction is executed in high-speed mode with the SBYCR SSBY bit = 1,
LPWRCR DTON bit = 1, LSON bit = 1, and TCSR_1 (WDT_1) PSS bit = 1, CPU operation shifts
to sub-active mode. When an interrupt occurs in watch mode, and if the LSON bit of LPWRCR is
1, a transition is made to sub-active mode. And if an interrupt occurs in sub-sleep mode, a
transition is made to sub-active mode.
In sub-active mode, the CPU operates at low speed on the subclock, and the program is executed
step by step. Peripheral modules other than PBC * , TMR_0, TMR_1, TMR_2 to TMR_4 * ,
WDT_0, WDT_1, and LCD are also stopped.
When operating the CPU in sub-active mode, the SCKCR SCK2 to SCK0 bits must be set to 0.
Note: * Supported only by the H8S/2268 Group.
22.9.2
Sub-active mode is exited by the SLEEP instruction or the RES or STBY pins.
• Exiting Sub-Active Mode by SLEEP Instruction
• Exiting Sub-Active Mode by RES Pins
• Exiting Sub-Active Mode by STBY Pin
Rev. 5.00 Sep. 01, 2009 Page 568 of 656
REJ09B0071-0500
When the SLEEP instruction is executed with the SBYCR SSBY bit = 1, LPWRCR DTON bit
= 0, and TCSR_1 (WDT_1) PSS bit = 1, the CPU exits sub-active mode and a transition is
made to watch mode. When the SLEEP instruction is executed with the SBYCR SSBY bit = 0,
LPWRCR LSON bit = 1, and TCSR (WDT_1) PSS bit = 1, a transition is made to sub-sleep
mode. Finally, when the SLEEP instruction is executed with the SBYCR SSBY bit = 1,
LPWRCR DTON bit = 1, LSON bit = 0, and TCSR (WDT_1) PSS bit = 1, a direct transition is
made to high-speed mode (SCK0 to SCK2 all 0).
For exiting sub-active mode by the RES pins, see section 22.4.2, Clearing Software Standby
Mode.
When the STBY pin level is driven low, a transition is made to hardware standby mode.
Sub-Active Mode
Transition to Sub-Active Mode
Exiting Sub-Active Mode
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