DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 548
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 18 DTMF Generation Circuit
18.3.2
The DTLR sets the system clock division ratio for the DTMF generation circuit.
Note: The correct values should be set in DTL0 to DTL5. If these bit settings do not match the
Rev. 5.00 Sep. 01, 2009 Page 496 of 656
REJ09B0071-0500
Bit
7, 6
5
4
3
2
1
0
system clock, correct DTMF signal output frequency cannot be obtained. Additionally,
correct operation is not guaranteed if the DTL0 to DTL5 settings are other than 5 to 51
(division ratio 5 to 51).
—
Bit Name
DTL5
DTL4
DTL3
DTL2
DTL1
DTL0
DTMF Load Register (DTLR)
Initial
Value
All 1
0
0
0
0
0
0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1 and cannot be modified.
Main clock division ratio 5 to 0
These bits set the system clock division ratio to produce
400-kHz clock signals to be supplied to the DTMF
generation circuit. The division ratio determines the
counter value of 6b'000101 to 6b'110011(D'5 to D'51)
according to the range 2.0 to 20.4 MHz.
000000: Setting prohibited
000001: Setting prohibited
000010: Setting prohibited
000011: Setting prohibited
000100: Setting prohibited
000101: Division ratio (5) main clock frequency (2.0 MHz)
000110: Division ratio (6) main clock frequency (2.4 MHz)
000111: Division ratio (7) main clock frequency (2.8 MHz)
110001: Division ratio (49) main clock frequency (19.6
110010: Division ratio (50) main clock frequency (20.0
110011: Division ratio (51) main clock frequency (20.4
110100: Setting prohibited
111111: Setting prohibited
:
:
MHz)
MHz)
MHz)
:
:
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