DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 114

IC H8S/2266 MCU FLASH 100-TQFP

DF2266TF13V

Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of DF2266TF13V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 4 Exception Handling
Figures 4.1 shows an example of the reset sequence.
4.3.2
If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: SP).
4.3.3
After reset release, MSTPCRA is initialized to H'3F, MSTPCRB to MSTPCRD are initialized to
H'FF, and all modules except the DTC (only for the H8S/2268 Group) enter module stop mode.
Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when the module stop mode is exited.
Rev. 5.00 Sep. 01, 2009 Page 62 of 656
REJ09B0071-0500
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)
Interrupts after Reset
State of On-Chip Peripheral Modules after Reset Release
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
φ
RES
(1)
Vector fetch
(2)
High
(4)
Internal
processing
(3)
Prefetch of first
program instruction
(5)
(6)

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