DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 338
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 11 8-Bit Timers
• Write to TLR
• Operation Clock
• Automatic Reload Function Select and Operation Timing
Rev. 5.00 Sep. 01, 2009 Page 286 of 656
REJ09B0071-0500
For a word connection, access in word units.
When writing to the cascaded TLR, even if a single channel of TLR is written, the system
regards that the entire channels of the cascaded TLR are rewritten. At this point in time, the
value in the entire cascaded TLR is loaded into the corresponding TCNT. The timer operation
starts at the TLR value that is most-recently written in TLR access cycles.
Although each channel usually operates on an individual clock, a cascaded channel operates on
the same clock. The operation clock for the lowest cascaded channel is used as a common
clock of each channel.
In this case, the setting for the clocks of the channels other than the lowest channel is disabled.
Figure 11.16 Channel Relationship of Cascaded Connection
1
2
3
4
5
6
7
8
Upper
Channel 4
Channel 4
Channel 4
Channel 4
Channel 4
Channel 4
Channel 4
Channel 4
Cascaded connection
Channel 5
Channel 5
Channel 5
Channel 5
Channel 5
Channel 5
Channel 5
Channel 5
Channel 6
Channel 6
Channel 6
Channel 6
Channel 6
Channel 6
Channel 6
Channel 6
Channel 7
Channel 7
Channel 7
Channel 7
Channel 7
Channel 7
Channel 7
Channel 7
Lower
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