DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 309
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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TIMH220B_000020020700
The H8S/2268 Group has an on-chip 8-bit timer module with four channels (TMR_0, TMR_1,
TMR_2 and TMR_3) operating on the basis of an 8-bit counter and an 8-bit reload timer with four
channels (TMR_4). The H8S/2264 Group has an on-chip 8-bit timer module with two channels
(TMR_0 and TMR_1) operating on the basis of an 8-bit counter.
11.1
The 8-bit timer module can be used to count external events and be used as a multifunction timer
in a variety of applications, such as generation of counter reset, interrupt requests, and pulse
output with an arbitrary duty cycle using a compare-match signal with two registers.
11.1.1
• Selection of clock sources
• Selection of three ways to clear the counters
• Timer output controlled by two compare-match signals
• Cascading of the two channels
• Multiple interrupt sources for each channel
• Generation of A/D conversion start trigger
• Module stop mode can be set
Note: * Supported only by the H8S/2268 Group.
Selected from three internal clocks (φ/8, φ/64, and φ/8192) and an external clock.
The counters can be cleared on compare-match A or B, or by an external reset signal.
The timer output signal in each channel is controlled by two independent compare-match
signals, enabling the timer to be used for various applications, such as the generation of pulse
output or PWM output with an arbitrary duty cycle.
The module can operate as a 16-bit timer using channel 0 (channel 2 * ) as the upper half and
channel 1 (channel 3 * ) as the lower half (16-bit count mode).
Channel 1 (channel 3 * ) can be used to count channel 0 (channel 2 * ) compare-match
occurrences (compare-match count mode).
Two compare-match interrupts and one overflow interrupt can be requested independently.
Channel 0 compare-match signal can be used as the A/D conversion start trigger.
At initialization, the 8-bit timer operation is halted. Register access is enabled by canceling the
module stop mode.
8-Bit Timer Module (TMR_0, TMR_1, TMR_2, and TMR_3)
Features
Section 11 8-Bit Timers
Rev. 5.00 Sep. 01, 2009 Page 257 of 656
Section 11 8-Bit Timers
REJ09B0071-0500
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