DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 364
![IC H8S/2266 MCU FLASH 100-TQFP](/photos/12/29/122926/df2266tf13v_sml.jpg)
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 13 Serial Communication Interface (SCI)
Note: etu (Elementary Time Unit): Abbreviation for the transfer period for one bit.
Rev. 5.00 Sep. 01, 2009 Page 312 of 656
REJ09B0071-0500
5
Bit
4
3
2
1
0
Bit Name
PE
O/E
BCP1
BCP0
CKS1
CKS0
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to transmit
data in transmission, and the parity bit is checked in
reception. In Smart Card interface mode, this bit must be
set to 1.
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
For details on setting this bit in Smart Card interface
mode, refer to section 13.7.2, Data Format (Except for
Block Transfer Mode).
Basic Clock Pulse 0 and 1
These bits specify the number of basic clock periods in a
1-bit transfer interval on the Smart Card interface.
00: 32 clock (S = 32)
01: 64 clock (S = 64)
10: 372 clock (S = 372)
11: 256 clock (S = 256)
For details, refer to section 13.7.4, Receive Data
Sampling Timing and Reception Margin in Smart Card
Interface Mode. S stands for the value of S in BRR (see
section 13.3.9, Bit Rate Register (BRR)).
Clock Select 0 and 1
These bits select the clock source for the baud rate
generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relationship between the bit rate register setting
and the baud rate, see section 13.3.9, Bit Rate Register
(BRR). n is the decimal representation of the value of n in
BRR (see section 13.3.9, Bit Rate Register (BRR)).
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