DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 151

• Manufacturer Part Number: DF2266TF13V
• Description: IC H8S/2266 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2266TF13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Interrupt controller of DTC control has the following three main functions.
Interrupt source selection: For interruption source, select DTC activation request or CPU
interruption request by the DTCE bits in DTCERA to DTCERF, and DTCERI of the DTC. After
DTC data transfer, the DTCE bit is cleared to 0, and an interrupt request to the CPU can be made
by the setting of the DISEL bit in MRB of the DTC. When DTC performs data transfer for
prescribed number of times and transfer counter becomes 0, the DTCE bit should be cleared to 0
and an interrupt request to the CPU is made after DTC data transfer.
Priority determination: DTC activation source is selected according to priority of default setting.
Mask level and priority level do not affect the selection. For details, see section 8.4, Location of
Register Information and DTC Vector Table.
Operation order: When the same interrupts are selected as DTC activation source and CPU
interruption source, DTC data is transferred, and then CPU interrupt exception processing is made.
Table 5.9 shows interrupt source selection and interrupt source clear control by the setting of the
DTCE bit in DTCERA to DTCERF, and DTCERI of the DTC and the setting of the DISEL bit in
MRB of the DTC.
IRQ
interrupt
On-chip
peripheral
module
Interrupt request
Interrupt source
clear signal
Interrupt controller
Figure 5.12 DTC and Interrupt Controller
Selection
DTVECR
DTCER
circuit
Selection
signal
SWDTE
clear signal
Clear signal
Rev. 5.00 Sep. 01, 2009 Page 99 of 656
determination
Control
Priority
logic
Section 5 Interrupt Controller
DTC activation
request vector
number
CPU interrupt
request vector
number
Clear signal
I, I2 to I0
REJ09B0071-0500
DTC
CPU