DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 466

• Manufacturer Part Number: DF2266TF13V
• Description: IC H8S/2266 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2266TF13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
The procedure for receiving data sequentially, using the wait states (WAIT bit) for
synchronization with ICDR (ICDRR) read operations, is described below.
The procedure below describes the operation for receiving multiple bytes. Note that some of the
steps are omitted when receiving only 1 byte. Refer to figure 14.11 for details.
Rev. 5.00 Sep. 01, 2009 Page 414 of 656
REJ09B0071-0500
Figure 14.11 Flowchart for Master Receive Mode (Receiving 1 Byte) (WAIT = 1)
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
No
No
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Set ACKB = 0 (ICSR)
Set ACKB = 1 (ICSR)
Set WAIT = 1 (ICMR)
Set WAIT = 0 (ICMR)
Master receive mode
and SCP = 0 (ICCR)
Set TRS = 0 (ICCR)
Set TRS = 1 (ICCR)
Write BBSY = 0
Read ICDR
Read ICDR
IRIC = 1?
IRIC = 1?
End
Yes
Yes
(Example)
[1]
[2]
[3]
[7]
[9]
[11] Clear IRIC flag (cancel wait state).
[12] Wait for end of reception of 1 byte.
[15] Cancel wait mode
[16] Read final receive data.
[17] Generate stop condition.
Set to receive mode
Receive start, dummy read.
Receive wait state (IRIC set at falling edge
of 8th clock cycle)
Set acknowledge data for final receive.
Set TRS to generate stop condition.
(IRIC set at rising edge of 9th clock cycle)
Clear IRIC flag. (IRIC flag should be
cleared when WAIT = 0.)