DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 488

• Manufacturer Part Number: DF2266TF13V
• Description: IC H8S/2266 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2266TF13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 I
9. Notes on I
10. Notes on IRIC Flag Clearance When Using Wait Function
Rev. 5.00 Sep. 01, 2009 Page 436 of 656
REJ09B0071-0500
If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance
is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising
of the 9th SCL clock, issue the stop condition after reading SCL and determining it to be low,
as shown below.
If the SCL rise time exceeds the designated duration or if the slave device is of the type that
keeps SCL low and applies a wait state when the wait function is used in the master mode of
the I
low, as shown below.
Clearing the IRIC flag to 0 when WAIT is set to 1 and SCL is being held at high level can
cause the SDA value to change before SCL goes low, resulting in a start condition or stop
condition being generated erroneously.
SDA
IRIC
SCL
2
C bus interface, read SCL and clear the IRIC flag after determining that SCL has gone
2
SCL
SDA
IRIC
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
2
C Bus Interface Stop Condition Instruction Issuance
VIH
Figure 14.24 IRIC Flag Clearance in WAIT = 1 Status
9th clock
Figure 14.23 Timing of Stop Condition Issuance
[1] Determination of SCL = Low
As waveform rise is late,
SCL is detected as low
V
SCL = low detected
[1] Judgement that SCL = low [2] IRIC clearance
IH
High period secured
SCL = high duration
maintained
[2] Stop condition instruction isuuance
Stop condition