DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 25

• Manufacturer Part Number: DF2266TF13V
• Description: IC H8S/2266 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2266TF13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.5
5.6
Section 6 PC Break Controller (PBC) ...............................................................103
6.1
6.2
6.3
6.4
5.4.3
Operation.............................................................................................................................88
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
5.5.6
Usage Notes ...................................................................................................................... 100
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
Features ............................................................................................................................. 103
Register Descriptions ........................................................................................................ 104
6.2.1
6.2.2
6.2.3
6.2.4
Operation........................................................................................................................... 106
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
Usage Notes ...................................................................................................................... 109
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
Interrupt Exception Handling Vector Table...........................................................84
Interrupt Control Modes and Interrupt Operation ..................................................88
Interrupt Control Mode 0 .......................................................................................92
Interrupt Control Mode 2 (H8S/2268 Group Only) ...............................................94
Interrupt Exception Handling Sequence ................................................................95
Interrupt Response Times ......................................................................................97
DTC Activation by Interrupt (H8S/2268 Group Only) ..........................................98
Contention between Interrupt Generation and Disabling..................................... 100
Instructions that Disable Interrupts ...................................................................... 101
When Interrupts Are Disabled ............................................................................. 101
Interrupts during Execution of EEPMOV Instruction.......................................... 102
IRQ Interrupt........................................................................................................ 102
NMI Interrupt Usage Notes.................................................................................. 102
Break Address Register A (BARA) ..................................................................... 104
Break Address Register B (BARB)...................................................................... 105
Break Control Register A (BCRA) ...................................................................... 105
Break Control Register B (BCRB)....................................................................... 106
PC Break Interrupt Due to Instruction Fetch ....................................................... 106
PC Break Interrupt Due to Data Access............................................................... 107
Notes on PC Break Interrupt Handling ................................................................ 107
Operation in Transitions to Power-Down Modes ................................................ 107
When Instruction Execution Is Delayed by One State ......................................... 108
Module Stop Mode Setting .................................................................................. 109
PC Break Interrupts.............................................................................................. 109
CMFA and CMFB ............................................................................................... 109
PC Break Interrupt when DTC Is Bus Master...................................................... 109
PC Break Set for Instruction Fetch at Address Following BSR, JSR, JMP,
TRAPA, RTE, or RTS Instruction ....................................................................... 109
I Bit Set by LDC, ANDC, ORC, or XORC Instruction ....................................... 110
PC Break Set for Instruction Fetch at Address Following Bcc Instruction.......... 110
PC Break Set for Instruction Fetch at Branch Destination Address of
Bcc Instruction ..................................................................................................... 110
Rev. 5.00 Sep. 01, 2009 Page xxiii of l
REJ09B0071-0500