DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 165

• Manufacturer Part Number: DF2266TF13V
• Description: IC H8S/2266 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2266TF13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.2
The Bus Controller has a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and DTC, which perform read/write operations when they
control the bus.
7.2.1
Each bus master requests the bus by means of a bus request signal. The bus arbiter detects the bus
masters’ bus request signals, and if the bus is requested, sends a bus request acknowledge signal to
the bus master making the request. If there are bus requests from more than one bus master, the
bus request acknowledge signal is sent to the one with the highest priority. When a bus master
receives the bus request acknowledge signal, it takes possession of the bus until that signal is
canceled.
The order of priority of the bus masters is as follows:
Figure 7.3 On-Chip Peripheral Module Access Cycle (H'FFFC30 to H'FFFCA3)
(High)
Bus Arbitration (H8S/2268 Group Only)
Order of Priority of the Bus Masters
φ
Internal address bus
Read
access
Write
access
DTC
Internal read signal
Internal data bus
Internal write signal
Internal data bus
>
CPU
(Low)
T1
Rev. 5.00 Sep. 01, 2009 Page 113 of 656
T2
Address
Bus cycle
Write data
T3
Read data
Section 7 Bus Controller
T4
REJ09B0071-0500