DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 476
DF2266TF13V
Manufacturer Part Number
DF2266TF13V
Description
IC H8S/2266 MCU FLASH 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet
1.DF2266TF20V.pdf
(712 pages)
Specifications of DF2266TF13V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
13MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
LCD, POR, PWM, WDT
Number Of I /o
67
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 14 I
7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in
8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode.
9. Dummy-read ICDR to release SDA on the slave side.
10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL
Rev. 5.00 Sep. 01, 2009 Page 424 of 656
REJ09B0071-0500
User processing
(master output)
(master output)
(slave output)
(slave output)
the ACKB bit to 0.
is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. At the
same time, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0.
To restart slave transmit mode operation, make the initial settings once again.
ICDRT
TDRE
ICDRS
SDA
SDA
IRIC
SCL
SCL
Figure 14.18 Example of Slave Transmit Mode Operation Timing (MLS = 0)
Slave receive mode
R/W
[3] IRIC clearance
2
C Bus Interface (IIC) (Supported as an Option by H8S/2264 Group)
8
9
A
[2]
Slave transmit mode
[3] ICDR write
Bit 7
1
Bit 6
2
[3] IRIC clearance
Bit 5
3
Bit 4
Data 1
4
Data 1
Data 1
Bit 3
5
Bit 2
6
Bit 1
7
Bit 0
8
9
[4]
A
[5] ICDR write
[5] IRIC clearance
Data 2
Data 2
Bit 7
1
Data 2
Bit 6
2
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