DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 608

• Manufacturer Part Number: DF2266TF13V
• Description: IC H8S/2266 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2266TF13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 Power-Down Modes
22.1
The following registers relates to the power-down modes. For details on system clock control
register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR). For details
on low power control register (LPWRCR), refer to section 21.1.2, Low Power Control Register
(LPWRCR). For details on timer control status register (TCSR_1), refer to section 12.2.2, Timer
Control/Status Register (TCSR).
• Standby control register (SBYCR)
• Module stop control register A (MSTPCRA)
• Module stop control register B (MSTPCRB)
• Module stop control register C (MSTPCRC)
• Module stop control register D (MSTPCRD)
• Low power control register (LPWRCR)
• System clock control register (SCKCR)
• Timer control status register (TCSR_1)
22.1.1
SBYCR performs power-down mode control.
Rev. 5.00 Sep. 01, 2009 Page 556 of 656
REJ09B0071-0500
7
Bit
Bit Name
SSBY
Standby Control Register (SBYCR)
Register Description
Initial
Value
0
R/W
R/W
Description
Software Standby
Specifies transition destination when the SLEEP
instruction is executed.
0: Shifts to sleep mode when the SLEEP instruction is
1: Shifts to software standby mode, sub-active mode, and
Note that the value of the SSBY bit does not change even
when software standby mode is canceled and making
normal operation mode transition by executing an
external interrupt. To clear this bit, 0 should be written to.
executed in high-speed mode or medium-speed mode.
Shifts to sub-sleep mode when the SLEEP instruction
is executed in sub-active mode.
watch mode when the SLEEP instruction is executed
in high-speed mode or medium-speed mode.
Shifts to watch mode or high-speed mode when the
SLEEP instruction is executed in sub-active mode.