DF2266TF13V Renesas Electronics America, DF2266TF13V Datasheet - Page 618

• Manufacturer Part Number: DF2266TF13V
• Description: IC H8S/2266 MCU FLASH 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of DF2266TF13V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: LCD, POR, PWM, WDT
• Number Of I /o: 67
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 Power-Down Modes
22.7
22.7.1
CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-
speed mode or sub-active mode with SBYCR SSBY=1, LPWRCR DTON = 0, and TCSR_1
(WDT_1) PSS = 1.
In watch mode, the CPU is stopped and peripheral modules other than WDT_1, TMR_4 * , and
LCD are also stopped. The contents of the CPU’s internal registers, the data in internal RAM, and
the statuses of the internal peripheral modules (excluding the A/D converter) and I/O ports are
retained. To make a transition to watch mode, bits SCK2 to SCK0 in SCKCR must be set to 0.
Note: * Supported only by the H8S/2268 Group.
22.7.2
Watch mode is exited by any interrupt (WOVI1 interrupt, OVI4 to OVI7 interrupts * , NMI pin, or
IRQ0, IRQ1, IRQ3, IRQ4, IRQ5 * , or WKP0 to WKP7), or signals at the RES, or STBY pins.
• Exiting Watch Mode by Interrupts
• Exiting Watch Mode by RES pins
• Exiting Watch Mode by STBY pin
Note: * Supported only by the H8S/2268 Group.
Rev. 5.00 Sep. 01, 2009 Page 566 of 656
REJ09B0071-0500
When an interrupt occurs, watch mode is exited and a transition is made to high-speed mode or
medium-speed mode when the LPWRCR LSON bit = 0 or to sub-active mode when the LSON
bit = 1. When a transition is made to high-speed mode, a stable clock is supplied to all LSI
circuits and interrupt exception processing starts after the time set in SBYCR STS2 to STS0
has elapsed. In the case of IRQ0, IRQ1, IRQ3, IRQ4, IRQ5 * , and WKP0 to WKP7 interrupts,
no transition is made from watch mode if the corresponding enable bit/pin function switching
bit has been cleared to 0, and, in the case of interrupts from the internal peripheral modules, the
interrupt enable register has been set to disable the reception of that interrupt, or is masked by
the CPU.
See section 22.4.3, Oscillation Settling Time after Clearing Software Standby Mode, for how
to set the oscillation settling time when making a transition from watch mode to high-speed
mode.
For exiting watch mode by the RES pins, see section 22.4.2, Clearing Software Standby Mode.
When the STBY pin level is driven low, a transition is made to hardware standby mode.
Watch Mode
Transition to Watch Mode
Exiting Watch Mode