S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 85

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

is loaded with valid data from the D-Flash EEE partition. Completion of this phase is indicated by the
CCIF flag in the FTM FSTAT register becoming set. If the CPU accesses any EEE RAM location before
the CCIF flag is set, the CPU is stalled until the FTM reset sequence is complete and the EEE RAM data
is valid. Once the CCIF flag is set, indicating the end of this phase, the EEE RAM can be accessed without
impacting the CPU and FTM commands can be executed.
1.6.3.3
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.
1.6.3.4
Refer to the PIM block description for reset configurations of all peripheral module ports.
1.6.3.5
The RAM arrays are not initialized out of reset.
1.6.3.6
The COP timeout rate bits CR[2:0] and the WCOP bit in the COPCTL register are loaded on rising edge
of RESET from the Flash register FOPT. See
loaded from the Flash configuration field byte at global address $7FFF0E during the reset sequence.
If the MCU is secured the COP timeout rate is always set to the longest period (CR[2:0] = 111) after COP
reset.
Freescale Semiconductor
Reset While Flash Command Active
I/O Pins
Memory
COP Configuration
FOPT Register
FOPT Register
MC9S12XE-Family Reference Manual Rev. 1.25
NV[2:0] in
Table 1-15. Initial COP Rate Configuration
NV[3] in
Table 1-16. Initial WCOP Configuration
000
001
010
011
100
101
110
111
1
0
Table 1-15
and
COPCTL Register
COPCTL Register
Table 1-16
CR[2:0] in
WCOP in
111
110
101
100
011
010
001
000
0
1
Chapter 1 Device Overview MC9S12XE-Family
for coding. The FOPT register is
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