S912XEP768J5MAGR Freescale Semiconductor, S912XEP768J5MAGR Datasheet - Page 384

• Manufacturer Part Number: S912XEP768J5MAGR
• Description: 16-bit Microcontrollers - MCU 16-bit 768K Flash
• Manufacturer: Freescale Semiconductor

Specifications of S912XEP768J5MAGR

• Rohs: yes
• Core: HCS12X
• Processor Series: MC9S12
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 768 KB
• Data Ram Size: 48 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.3 V to 5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-144
• Mounting Style: SMD/SMT

Chapter 10 XGATE (S12XGATEV3)
10.8.1.8
In this mode the result of an operation between two registers is stored in one of the registers used as
operands.
RD = RD ∗ RS is the general register to register format, with register RD being the first operand and RS
the second. RD and RS can be any of the 8 general purpose registers R0 … R7. If R0 is used as the
destination register, only the condition code flags are updated. This addressing mode is used only for shift
operations with a variable shift value
Examples:
10.8.1.9
In this mode the result of an operation between two or three registers is stored into a third one.
RD = RS1 ∗ RS2 is the general format used in the order RD, RS1, RS1. RD, RS1, RS2 can be any of the
8 general purpose registers R0 … R7. If R0 is used as the destination register RD, only the condition code
flags are updated. This addressing mode is used for all arithmetic and logical operations.
Examples:
10.8.1.10 Relative Addressing 9-Bit Wide (REL9)
A 9-bit signed word address offset is included in the instruction word. This addressing mode is used for
conditional branch instructions.
Examples:
10.8.1.11 Relative Addressing 10-Bit Wide (REL10)
An 10-bit signed word address offset is included in the instruction word. This addressing mode is used for
the unconditional branch instruction.
Examples:
10.8.1.12 Index Register plus Immediate Offset (IDO5)
(RS, #OFFS5) provides an unsigned offset from the base register.
Examples:
384
LSL
LSR
ADC
SUB
BCC
BEQ
BRA
LDB
STW
Dyadic Addressing (DYA)
Triadic Addressing (TRI)
R4,R5
R4,R5
R5,R6,R7
R5,R6,R7
REL9
REL9
REL10
R4,(R1,#OFFS5)
R4,(R1,#OFFS5)
; R4 = R4 << R5
; R4 = R4 >> R5
MC9S12XE-Family Reference Manual Rev. 1.25
; R5 = R6 + R7 + Carry
; R5 = R6 - R7
; PC = PC + 2 + (REL9 << 1)
; PC = PC + 2 + (REL9 << 1)
; PC = PC + 2 + (REL10 << 1)
; loads a byte from (R1+OFFS5) into R4
; stores R4 as a word to (R1+OFFS5)
Freescale Semiconductor